Systems of chips may be designed to be interconnected, for example in prototypes of large ASIC designs built using more than one field programmable gate array (FPGA). In some systems it is acceptable to connect the chips using a communications protocol, such as Ethernet, in which the interface is recognized by initiators of data transfers, such as processors. In other systems it is beneficial, for reasons such as encoding and decoding latency, to use a communications protocol that is transparent to initiators by using a single address space fixed in the hardware of both chips.
Some interconnection networks of initiators and targets use packet based protocols because of physical implementation benefits. Compared to traditional transaction interfaces, packet based networks require less decoding logic and therefore faster signal propagation through the logic of the network topology. Furthermore, packetizing gives the ability to change data serialization with less logic area and long timing paths through logic.
Packet based networks also give the ability to easily add pipeline stages in data paths in order to break long timing delays between flops. Paths that propagate on a printed circuit board between chips are generally very slow compared to paths within a chip. Therefore it is desirable to have a layer of registers immediately at the outputs of one chip and the connected inputs of the other chip without any combinatorial logic in between the registers. This is particularly the case when the chips are FPGAs, which generally have special high speed input an output registers that can not be used if there is combinatorial logic between a register and an IO in the design.
In state of the art on-chip communication protocols, data flows forward from an upstream sender with a sideband signal indicating when the data signal is valid. A corresponding handshake signal flows backward to indicate that the downstream receiver is ready to receive the data. Pipeline registers can be added within the path to partition timing critical logic paths. One problem is that pipeline stage registers in the direction of data flow divide long timing paths on all forward going paths but not on the paths of backward going flow control signals. See FIG. 1 register 101. To pipeline a backward going Ready signal, as with the register 201 in FIG. 2, a register must store the data, as in register 202, from the previous cycle as the ready signal propagates backwards. This creates a combinatorial control path from the backward going Ready signal into the forward going logic. As a result, no combination of forward-going and backward-going pipe stages can avoid all combinatorial logic between registers at the IOs of chips. Therefore, what is needed is a system and method to provide registered inputs and output in a multi-chip systems.